German processor design company Codasip has donated its latest RISC-V software development kit to chip security consortium CHERI Alliance to help developers add memory safety to chips.
RISC-V is an instruction set architecture (ISA) that allows developers and manufacturers to personalize silicon chips with capabilities to meet their needs, such as for use in smartphones, space technologies, industrial applications, and automotive technologies, to name a few. RISV-V is open and free to license, so anyone can design, manufacture, and sell RISC-V chips and software.
CHERI (Capability Hardware Enhanced RISC Instructions) extends ISA to manage memory access control to prevent common vulnerabilities, such as buffer overflows and memory corruption. The method involves isolating the hardware and software so that adversaries cannot inject attack code into memory. The CHERI Alliance is an industry consortium focused on promoting the development and adoption of security technologies that protect data stored in hardware memory.
Developers need access to tools and packages that are available for CHERI — this is what the SDK that Codasip built and donated to the CHERI Alliance offers. The compiler is capable of generating the modified instructions. Anyone implementing CHERI on RISC-V chips can access the SDK, which is freely available on GitHub.
The SDK includes:
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C/C++ compiler and toolchain based on LLVM17
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CHERI-RISC-V Sail model
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QEMU open source emulator
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OpenSBI implementation of the RISC-V Supervisor Binary Interface
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Das U-Boot bootloader
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Linux kernel 6.10
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GNU Debugger
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Yocto build system for Linux
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Basic user space environment based on Busybox
“As more organizations and governments discover the potential of the CHERI technology to protect us, we need to speed up the pace of making the technology available in real systems,” Codasip CEO Ron Black said in a statement. “We have made a massive effort to implement a full Linux-capable SDK that we are now opening for everyone to use.”
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